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FPGA image processing
CXP-6 Single/Dual/Quad 1Ch configurable CoaXPress frame grabber

  • Intel FPGA Arria10 10AX066H2F34E2SG

  • Up to CXP-6 Quad configurable, Max. 25Gbit/s transmit with Quad link

  • Available Configuration :  CXP-6 Quad(1Ch), Dual(1Ch), Single(1Ch)

  • Check the status of the camera with the front panel LED

  • 2 GB of DDR3 memory as image buffer

  • Enables image input control by encoder signal input (RS – 422)

  • Equipped general purpose input / output pin (TTL or open collector) for I / F with external equipment

  • PCI Express 3.0 (Gen3) 8GT/s ×8, and when DMA, average 3.2GByte/s can be transmitted

Model APX-3664S4-PRO
Image input I/F CoaXPress Rev1.1
CXP-6Quad (25Gbit/s) x1 ※ 1 camera
CXP-6Dual (12.5Gbit/s) x1 ※ 1 cameras ※ Asynchronous
CXP-6 Single (6.25Gbit/s) x1 ※ 1 cameras ※ Asynchronous
DIN 1.0 / 2.3  4ea equipped (Arranged at 9mm interval)
Image input format Mono 8,10,12bit / RGB 8,10bit
Camera power output Power Over CoaXPress : + 24V (13W) x4 ※  + 24V voltage is generated within board
FPGA Image processing Support
Encoder RS-422 (Line driver)
Phase-A, B, Z  1MHz (MAX)
32bit counter and 32bit / 16bit compare register, one pair each installed
(Image input trigger with comparison register match)
General Purpose I / O D-Sub Connector
GP input : 8ch (TTL / Open collector / Exposure control · Sync input)
GP output: 4ch (TTL / Open collector / Flash user output)
RS-422 In : 4ch (Compabible with Shaft Encoder 3ch )
Event Image grab start, DMA end, GPIN, etc.,
FPGA Temp. monitoring Compatible
System BUS PCI Express3.0 (Gen3)×8  8.0GT/s
Power + 12V ± 8 % (External + 12V Connector)
Operating environment Temp. : 0 ℃ ~ 50 ℃,  Humidity : 30 ~ 85 % (Non-condensing)
Dimension 167.65mm x 111.15mm (Excluding connector)
OS Windows 10/7 (32bit/64bit)
SDK (Option) SDK-TransFlyer / SDK-AcapLib2
– The specifications and appearance stated are subject to change without notice.
– Power consumption does not include inrush current.
– In order to use the product correctly, be sure to read the instruction manual before using the product. Also, use the product under the conditions applicable to your product warranty.

패키지 내용
– Quartus Ⅱ 프로젝트 프로그램 소스 (VHDL) 세트 (※ 단, 보드 제어 부분은 모두 암호화)
– 범용 레지스터 액세스 도구
– 화상 처리 IP 제어 응용 프로그램

사용자 개발용 샘플 디자인 준비
– 레지스터 회로 – PLL
– 화상 처리 회로 – Reclocking

※ 제공하는 샘플 디자인은 개발 환경에 의존하는 부분이 있으므로, 개발 환경의 버전 등에 관해서는 별도 문의 바랍니다.