LVDS Interface image processing board
- One line or Area camera that supports the LVDS interface can be connected.
- synchronize and asynchronously capture is possible with the connected cameras.
- It has an external I / O interface, it is possible to link with external devices and generate interrupts.
- With strobe timing output, it is possible to notify the external lighting device of the exposure timing.
- MEGA – FIFO (*) As a picture buffer, 128 Mbytes capacity is implemented.
- With PCI Express 2.0 (Gen 2) 2.5 GT / s x 1, high-speed image capture is possible.
- Compatible with RoHS
|Image input||LVDS camera x 1 ch
Sampling clock: 1 KHz to 60 MHz
|External trigger||TTL / open collector
Image input start, encoder control, TTL interface (falling edge)
|Encoder||A, B, Z phase (RS-422)|
|interrupt||Input start / input end / FIFO error / DMA end|
|System bus||PCI Express 2.0 (Gen 2) 2.5 GT / s (Max) × 1|
|Current consumption||+ 12V 0.7A Max|
|usage environment||Temperature: 0 ℃ ~ 50 ℃
Humidity: 35% to 85% (no condensation)
|External dimensions||167.65 mm x 111.15 mm (without projections), panel width 20 mm|
|Supported OS||Windows (32-bit · 64 bit)|
|Environmental response||RoHS compliant|
– The specifications and appearance stated are subject to change without notice.
– The current consumption does not include inrush current.
– In order to use the product correctly, be sure to read the instruction manual before using the product. In addition, use the product under conditions applicable to the product warranty.
About the MEGA-FIFO architecture
The MEGA-FIFO temporarily stores the image data from the camera in the onboard large capacity buffer, and transfers it to the host memory. Hardware guarantees buffer input at the camera’s fastest operation. (The maximum data rate is 60 MHz x 32 bits = 240 MByte / sec.) Even when the bandwidth of PCI Express temporarily falls below the camera frame rate, you can input images until the buffer becomes full.