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APX-3307-260
CL Base x 2Ch, FPGA processing board
| Model | APX-3307-260 |
| Image input I / F | CameraLink Base Configuration 2ch Two SDR 26 pin connectors Sampling clock 85 MHz (MAX) Image data RGB color: 24 bits Monochrome: 8 (1/2/3 Tap) / 10/12 bit (1/2 Tap) |
| PoCL | Correspondence |
| MEGA-FIFO | DDR2-SDRAM 128MB |
| Memory | 387MB |
| FPGA | ALTERA EP2AGX260 |
| Sync output | Camera control signals: CC1 to CC4 General purpose output: 2 ch asynchronous, TTL / open collector (Available with the strobe timing output) |
| Sync input | External trigger: TTL / open collector / differential signal RS-422 Encoder: differential signal RS-422 (line driver), A / B / Z phase, 1 MHz (MAX) General purpose input: TTL / open collector |
| Interrupt | Image input start, DMA end, GPIN etc. |
| System bus | PCI Express 2.0 x4 (Gen2) 2.5GT / S |
| Power | + 12V |
| Environment | Temperature 0 ℃ to 50 ℃, humidity: 35% to 85% (no condensation) |
| Dimension | Low Profile 167.65 mm × 68.9 mm Panel width 20 mm (not including Projections) |
| OS | Windows 10 / 7 compatible with 32 bit / 64 bit, Linux |
| software (option) | SDK : SDK-AcapLib2 FDK : AZP-FDK APX-3307 |
Notes)
– The specifications and appearance stated are subject to change without notice.
– Power consumption does not include inrush current.
– In order to use the product correctly, be sure to read the instruction manual before using the product. Also, use the product under the conditions applicable to your product warranty.
– The specifications and appearance stated are subject to change without notice.
– Power consumption does not include inrush current.
– In order to use the product correctly, be sure to read the instruction manual before using the product. Also, use the product under the conditions applicable to your product warranty.
