APX-3664-E7
FPGA image processing CoaXPress Frame Grabber

  • 25Gbit/s high speed data transfer CXP-6 Quad link
  • Transfer video, control power supply with one coaxial cable
  • Check the state of the camera with the front panel LED
  • 2 GB of DDR 3 memory as image buffer
  • Image input control by encoder signal input
  • External trigger available for acquisition control/encoder operation
  • GPIO for use of external device
  • Intel FPGA installed for custom image processing
  • PCIE 2.0 (5.0GT/s) x8 compatible, DMA data transfer speed 3.2GB/s (average)
Model APX-3664A-E7
Image input I / F Coaxpress
Rev 1.1
CXP – 6 Quad (25 Gbit / s) x 1 * 1 Camera connection
CXP – 6 Dual (12.5 Gbit / s) x 1 * 1 Camera connection
CXP – 6 Single (6.25 Gbit / s) x 1 * 1 Camera connection
Four DIN 1.0 / 2.3 installed (arranged at 9 mm intervals)
Image input data 8, 10, 12 bit monochrome / RGB
Camera power output Power Over Coaxpress: +24 V (13 W) x 4
* +24 V voltage generation inside the board
Onboard memory DDR3 SO-DIMM 2GB
FPGA image processing Present
General purpose I / O SDR connector General-purpose input: 8 ch
(TTL / open collector exposure control / synchronous input)
General purpose output: 4 ch
(TTL / open collector strobe user output)
RS-422 input: 4 ch
interrupt Image input start, DMA end, GPIN etc.
FPGA temperature monitoring Present
System bus PCI-Express 2.0 x 8 lane (Gen 2) 5.0 GT / S
Power supply + 12 V ± 8% (PCI – Express connector)
+ 12 V ± 8% (External connector: exclusively for PoCXP)
usage environment Temperature: 0 ℃ ~ 50 ℃, Humidity: 30 ~ 85% (no condensation)
External dimensions 183.00 mm × 111.15 mm, panel width 20 mm
Supported OS Windows
Software (option) Development kit :: SDK-TransFlyer / SDK-AcapLib2
FPGA Development Kit: FDK-APX3664A-E7
Notes)
– The specifications and appearance stated are subject to change without notice.
– The current consumption does not include inrush current.
– In order to use the product correctly, be sure to read the instruction manual before using the product. In addition, use the product under conditions applicable to the product warranty.

Quartus II project · Complete program source (VHDL)
(※ However, all board control parts are encrypted)
· General purpose register access tool
· Image processing IP control application

Sample design for user development
.Register circuit
· PLL
Image processing circuit
· Reclocking

* Since the development environment for sample design depends on the development environment, please contact the development environment version separately.